A RAS input disable (RID) circuit determines when the DRAM circuits are ready to accept RAS.sub.-- clock for memory access. Before these DRAM circuits can be activated by accepting the RAS.sub.-- clock signals, two voltage levels are checked. One of these levels is the internal positive supply level and the other is the internal back bias level V.sub.BB. The RID circuit should ascertain that the internal supply is stable and determine that the V.sub.BB level is sufficiently low. As the portable computer becomes increasingly popular, one concern of the designers of these portable computers has been to reduce the power consumption of DRAM circuits which is a major component of power use of the portable computer. The requirement to reduce the power consumption places constraints on standby current and self-refresh current. In order to assure proper low power operation, standby current should be minimized in that all circuits should be designed so that they do not draw any DC currents. In order for the RID circuit to properly provide a RID signal, both the internal power supply level and the internal back bias level V.sub.BB should be at satisfactory and predetermined levels before the RID signal is to be provided. The proper internal positive supply level may be detected by the Power Up Detector (PUD) circuit which provides a PUD signal to the RID circuit. However, before the RID circuit can provide the RID signal, once the PUD signal has been received, the internal back bias level must also be established.
There are two approaches to determine if the internal back bias level is at a predetermined level. One of these approaches is a DC level detection approach and the other a transient time-based approach. The DC level detection approach ensures an internal back bias level has been established which actually depends on the level of voltage V.sub.BB, and an example of this approach is illustrated in FIG. 1 and requires a small amount of DC current.
The inverter 102 inverts the PUD signal so that the output of the inverter 102 is high while the PUD signal is low, preventing a false RID signal from NOR gate 116. The remaining portion of the circuit detects the internal back bias level.
While voltage V.sub.BB is not sufficiently low for proper DRAM operations, transistor 106 is turned off, and the voltage at node 150 is raised to logically high level by P-channel transistor 104 since transistor 104 is turned on. Therefore, node 152 is initially logically low. Node 154 is set high as a result of inverter 114. Thus, after PUD is asserted high, the RID signal remains high until the voltage level at node 150 changes from high to low. Node 150 is reset to logically low when voltage V.sub.BB is at least one threshold voltage of an N-channel transistor, V.sub.TN, below ground by turning transistor 106 on sufficiently enough to overdrive the effect of transistor 104. Since both transistors 106 and 104 remain on after transistor 106 has been turned on, a DC current flows from the voltage supply through transistors 104 and 106 to voltage V.sub.BB. If this current is cut off by turning transistor 106 off then the RID signal will be set high again to inhibit further memory access. Clearly, in order to provide a stable RID signal, the transistors 104 and 106 must conduct current, resulting in power loss.
On the other hand, the transient time-based approach does not require DC current in order to provide a RID signal. However, the circuit employing the transient time-based does not measure the internal back bias level directly, but provides an approximation of the internal back bias level by a function of time. Thus, a disadvantage of the second approach is that there is no guarantee that the internal back bias level is at the proper level when the RID signal is generated.
FIG. 2 illustrates a RID circuit using this second approach. Initially, PUD is at logically low level when internal supply level is not yet established. Thus, the voltage at node 254 is charged to a high logical level by transistor 208 while transistor 206 is turned off. With node 254 being high transistor 211 is turned off, and the P-channel transistor 212 is turned on to output a high voltage at node 256. Through the inversion of transistors 216, 218 and inverter 224, a high RID is thus generated when PUD is low. As the PUD signal changes from low to high, node 254 is isolated from supply and is connected through transistor 206 to transistor 204. Since transistor 212 is also turned off, the status of node 256 is now determined solely by node 254. To change the high state at node 254, both N-channel transistors 200 and 204 must be turned on by the voltage V.sub.BB falling below ground such that the gate to source voltages of transistors 200 and 204 are more than the threshold voltage of the transistors 200 and 204. When this V.sub.BB voltage level is reached, transistors 200 and 204 are turned on to discharge node 254 to ground and consequently, node 256 goes to a logical low since transistor 212 is turned on. Thus when node 250 and node 254 go to ground, node 256 goes low indicating the disabled function is on.
Since there is no DC current path to node 254 after PUD is set high, the discharging of node 254 does not result in DC current. Hence, the detection of V.sub.BB is accomplished without consuming DC current.
Furthermore, since the logic state of node 254 is maintained by dynamic charge stored on capacitor 210, the exact switching point of the circuit varies as a function of the discharging current through transistors 200,204 and 206 as well as the capacitance of capacitor 210.